Huawei Releases Updated Chip Theory with Engineering Details
Huawei has released version 2 of its 'Tao Law' theory, introducing enhanced engineering details and test data for chip development. The theory focuses on time constant τ and aims to extend Moore's Law.
Chinese technology firm Huawei has released the second version of its foundational theory known as the 'Tao Law' (Taiming Theory), which addresses advanced semiconductor design. He Tingbo, head of Huawei Semiconductor, unveiled the V2 version on July 3rd via the ChinaXiv academic paper platform. This updated theory incorporates more detailed engineering blueprints, empirical measurement data, and product evolution roadmaps compared to its initial release.
The theory centers on the time constant τ (tau) and is presented as a framework for the post-Moore's Law era, aiming to enable scaling beyond traditional transistor shrinking. Version 2 elaborates on the theoretical structure, adding specific engineering implementations and quantitative performance data. Its goal is to establish a "time scaling" theory for multi-layer electronic systems.
The V2 release delves deeper into core technologies, such as the LogicFolding architecture. This approach shifts optimization from traditional macro-block discrete methods to continuous unit-level optimization, allowing for vertical logic partitioning in 3D chip stacking. The theory also outlines inter-chip connectivity through architectures like Unified Bus and the Hi-ONE optical engine.
Significantly, the V2 version includes actual mass production test data. It presents comparative metrics for the Kirin 2026 chip against a baseline Kirin 9030 Pro, detailing voltage, frequency, normalized power consumption, area, and power density. A detailed roadmap for future development in mobile and AI applications is also provided, outlining key technological advancements.