Huawei unveils new chip technology with vertical stacking
Huawei has launched its new Kirin 9050 Pro chip, utilizing "Logic Folding" technology by vertically stacking two dies. This increases transistor density and reduces power consumption.
Chinese technology firm Huawei has revealed its new Kirin 9050 Pro chip, employing "Logic Folding" technology. Semiconductor analysis firm Kurnal Insights released die shot images, showcasing the chip's internal structure: two identical dies are vertically stacked.
The new chip utilizes vertical stacking instead of traditional planar layouts. One die handles core computing logic, while the other is dedicated to SRAM and cache. This "Logic Folding" technique reduces signal propagation delays, allowing for a 55% increase in transistor density within a smaller area compared to the previous generation, even though the overall die area is reduced.
The chip incorporates SMIC's N+3 process for the logic die and an N+2 process for the SRAM die. While the smaller size of individual dies should improve yield, the overall package yield might still be constrained due to limited distribution. Reports suggest the Kirin 9050 Pro narrows Huawei's technology gap with Apple's mobile chips to approximately three years.
Huawei's Mate 90 Pro Max and Mate 90 RS models feature the Kirin 9050 Pro chip. The company reported significant system performance improvements compared to previous generation models. The new chip includes a 灵犀 (Lingxi) CPU, a 马良 (Maliang) GPU, and a Davinci architecture-based NPU, which supports large language models.