Intel Reportedly Considering Modified 14A2 Process to Address Power Delivery Challenges

Intel is reportedly evaluating a modified version of its upcoming 14A semiconductor manufacturing process, dubbed 14A2, to tackle technical challenges related to power delivery. The proposed change involves adopting a dual-sided power delivery system to ensure sufficient power reaches transistors in future, smaller nodes.

The original 14A process intended to utilize backside power delivery (BSPDN), moving power grids to the rear of the wafer. This would free up frontside metal layers for routing, thereby increasing transistor density and improving performance. However, the 14A2 process shrinks the minimum metal interconnect (M0) spacing to approximately 21nm from 14A's 28nm, a move intended to boost transistor density and leverage High-NA EUV lithography.

This reduction in M0 spacing increases interconnect wire resistance. As the wires become narrower, the nanometer Through-Silicon Via (nTSV) used in backside power delivery may struggle to deliver the required current density, leading to significant voltage drop issues. To mitigate this, Intel is considering a hybrid approach, retaining backside power delivery as the primary method while reintroducing some frontside metal layers for auxiliary power and clock signal distribution.

The 14A process is a key element in Intel's strategy to compete with advanced nodes from TSMC (N2, A14) and Samsung (SF2Z). Intel aims to release the 14A Process Design Kit (PDK) to external customers in October 2026, with high-volume production targeted for 2029. The semiconductor industry faces continuous pressure to shrink manufacturing processes, with challenges in defect control and interconnect reliability becoming increasingly prominent.