Nokia Details 4K HEVC Encoder on FPGA Accelerated Server
Nokia Bell Labs has published details of a new 4K Ultra HD HEVC encoder designed for real-time video streaming, utilizing FPGA acceleration.
Nokia Oyj's research arm, Bell Labs, has detailed a new real-time 4K Ultra HD HEVC (High Efficiency Video Coding) encoder implemented on a Field-Programmable Gate Array (FPGA) accelerated server. This development aims to enhance the efficiency and speed of high-definition video streaming.
The encoder is deployed on Nokia's AirFrame Cloud Server, which integrates Intel Xeon processors with an Arria 10 FPGA PCIe accelerator card. In this hybrid setup, data-intensive encoding tasks, including intra prediction and quantization, are offloaded to the FPGA. Control-intensive operations remain on the Xeon processors. The Arria 10 card supports up to two instances of the intra coding accelerator.
According to the published results, the system can encode 4K video at 30 frames per second with a single intra coding accelerator and at 40 frames per second when using two accelerators. This configuration reportedly offers speed-up factors of 1.6 and 2.1 over a pure Xeon implementation.
Nokia Bell Labs stated this is the first known work partitioning an HEVC intra encoder between a CPU and an FPGA. The company claims the solution achieves comparable speed to ASIC-based HEVC intra encoders and is significantly faster than existing FPGA HEVC intra encoders.