Samsung considers outsourcing Google TPU chip design backend work

Samsung Electronics is exploring the possibility of outsourcing some or all of the backend design work for the input/output (I/O) die of Google's upcoming 2-nanometer Tensor Processing Unit (TPU). Sources indicate this consideration stems from an escalating demand for Samsung's foundry services and a subsequent strain on its internal engineering capacity.

The new TPU, codenamed "Icefish," is designed to accelerate artificial intelligence models like Gemini. It will utilize Samsung's 2-nanometer process for the I/O die, while the main compute processor will be manufactured by TSMC using a 1.4-nanometer process. The I/O die plays a critical role in facilitating data transfer between the compute processor and High Bandwidth Memory (HBM).

The backend design tasks include physical implementation aspects such as logic circuit layout, routing, and design verification. Samsung has reportedly approached its Design Solution Partners (DSP) to gauge their interest in undertaking this work for Google's "Icefish" TPU. These partners specialize in optimizing chip designs for manufacturing on Samsung's foundry.

While Samsung previously handled such backend design processes internally, exemplified by its work on Tesla's autonomous driving chips, the recent surge in wafer fabrication orders for its leading-edge 2-nanometer process has stretched its engineering resources. The tight capacity at TSMC for advanced nodes has also reportedly shifted some orders towards Samsung.

Industry analysts identify ADTechnology and Gaonchips as the primary candidates for this outsourcing opportunity, as both are already involved in projects utilizing Samsung's 2-nanometer technology. However, both companies also have substantial existing workloads and may be hesitant to take on new projects that offer lower profit margins compared to complete ASIC development.