SK Hynix Unveils H-TPU Architecture for SSD Controllers

SK Hynix has unveiled its new H-TPU (Hynix Transaction Processing Unit) architecture, specifically designed to enhance SSD controllers. The technology, announced on October 12, aims to address the growing performance bottlenecks in data centers that are increasingly shifting to memory and storage layers with the proliferation of AI.

Gu In-jae, Senior Vice President of SoC Design at SK Hynix, noted that the capabilities of traditional general-purpose CPUs have reached their limits for the demanding tasks within SSD controllers. Current CPU architectures have proven inefficient for handling the hundreds of detailed functions required for storage management, leading to significant power consumption and unpredictable delays.

The H-TPU differs from traditional CPU solutions by being a programmable processor specialized for SSD data plane control and transaction processing. Instead of relying on a single, large general-purpose CPU, the H-TPU divides control functions into numerous small, specialized TPU clusters. This approach drastically reduces the chip's physical footprint and power consumption.

SK Hynix plans to implement H-TPU technology across its entire range of NAND memory products, including future enterprise SSD controllers and the "Storage Next" architecture. The company expects the new architecture to yield significant synergies when combined with the enhanced HBF (High Bandwidth Flash) memory, slated for release next year.